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NCP5623C
ANALOG SECTION:
(Typical values are referenced to T A = +25 ° C, Min & Max values are referenced ? 40 ° C to +85 ° C ambient temperature, unless otherwise
noted), operating conditions 2.85 V < Vbat < 5.5 V, unless otherwise noted.
Pin
8
8
Symbol
I REF
V REF
Rating
Reference current @Vref = 600 mV (Note 7)
Reference Voltage (Note 7)
Min
3
? 3%
Typ
12.5
600
Max
20
+3%
Unit
m A
mV
I LEDR
Reference Current (IREF) current ratio
2400
8
3,4,5
Rbias
F PWM
External Reference current Bias resistor (Note 6)
Internal PWM Frequency (Note 8)
30
48
2.1
200
k W
kHz
6. The overall output current tolerance depends upon the accuracy of the external resistor. Using 1% or better resistor is recommended.
7. The external circuit must not force the I REF pin voltage either higher or lower than the 600 mV specified. The system is optimized with a
12.5 m A reference current.
8. This parameter, derived from the 1 MHz clock, is guaranteed by design, not tested in production.
DIGITAL PARAMETERS SECTION:
(Typical values are referenced to T A = +25 ° C, Min & Max values are referenced ? 40 ° C to +85 ° C ambient temperature, unless otherwise
noted), operating conditions 2.85 V < Vbat < 5.5 V, unless otherwise noted.
Pin
9
7,9
Symbol
F SCL
V IH
Rating
Input I2C clock frequency
Positive going Input High Voltage Threshold,
Min
1.6
Typ
Max
400
V BAT
Unit
kHz
V
SDA, SCL signals (Note 9)
7,9
V IL
Negative going Input High Voltage Threshold,
0
0.4
V
SDA, SCL signals (Note 9)
NOTE: Digital inputs undershoot ≤ 0.30 V to ground, Digital inputs overshoot < 0.30 V to V BAT
9. Test guaranteed by design and fully characterized, not implemented in production.
10. The fall time ? t f ? for both SCL and SDA input signals must be 120 ns maximum.
The chip might be damaged or destroyed
Chip functionnal, but no parameter guaranteed
when Vbat is between 5.5 V & 7.0 V
7.0 V
5.5 V
when Vbat is above 7.0 V
Absolute Maximum Rating
Maximum Voltage Operation
4.2 V
NORMAL Li ? Ion OPERATION
3.0 V
2.7 V
2.0 V
Power On Reset
No operation during POR
Reserved for internal Reset
Figure 3. Understanding Integrated Circuit Voltage Limitations
http://onsemi.com
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